caa a22 4500 445820519 CHVBK 20180317145242.0 cr unu---uuuuu 170323e20110601xx s 000 0 eng 10.1007/s10825-011-0359-6 doi (NATIONALLICENCE)springer-10.1007/s10825-011-0359-6 Analysis of double-gate CMOS for double-pole four-throw RF switch design at 45-nm technology [Elektronische Daten] [Viranjay Srivastava, K. Yadav, G. Singh] In this paper, we have analyzed a 45-nm RF CMOS switch design technology with the double-pole four-throw circuit by using independently controlled double-gate MOSFET. The proposed switch reduces the number of transistors and increases the logic density per unit area as compare to the conventional CMOS switch. With the unique independent double-gate properties, we have demonstrated the potential advantages in terms of the drain current, threshold voltage, attenuation with ON resistance, flat-band capacitances, charge density and power dissipation of the proposed switch, which provides a switch with a significant drive circuit that is free from the signal propagation delay and additional voltage power supply. Moreover, the main emphasis is to provide a plurality of such switches arranged in a densely configured switch array, which provides a lesser attenuation, and better isolation with fast switching speed. Springer Science+Business Media LLC, 2011 45-nm technology nationallicence Double-gate MOSFET nationallicence DP4T switch nationallicence Radio frequency nationallicence RF switch nationallicence Attenuation nationallicence CMOS switch nationallicence VLSI nationallicence Srivastava Viranjay Department of Electronics and Communication Engineering, Jaypee University of Information Technology, 173234, Solan, India aut Yadav K. VLSI Design Group, Central Electronics Engineering Research Institute (CEERI), 333031, Pilani, India aut Singh G. Department of Electronics and Communication Engineering, Jaypee University of Information Technology, 173234, Solan, India aut Journal of Computational Electronics Springer US; http://www.springer-ny.com 10/1-2(2011-06-01), 229-240 1569-8025 10:1-2<229 2011 10 10825 https://doi.org/10.1007/s10825-011-0359-6 text/html Onlinezugriff via DOI 1 research-article jats NATIONALLICENCE 856 40 https://doi.org/10.1007/s10825-011-0359-6 text/html Onlinezugriff via DOI NATIONALLICENCE 700 1- Srivastava Viranjay Department of Electronics and Communication Engineering, Jaypee University of Information Technology, 173234, Solan, India aut NATIONALLICENCE 700 1- Yadav K. VLSI Design Group, Central Electronics Engineering Research Institute (CEERI), 333031, Pilani, India aut NATIONALLICENCE 700 1- Singh G. Department of Electronics and Communication Engineering, Jaypee University of Information Technology, 173234, Solan, India aut NATIONALLICENCE 773 0- Journal of Computational Electronics Springer US; http://www.springer-ny.com 10/1-2(2011-06-01), 229-240 1569-8025 10:1-2<229 2011 10 10825 Metadata rights reserved Springer special CC-BY-NC licence nationallicence BK010053 XK010053 XK010000 NATIONALLICENCE NATIONALLICENCE NL-springer