caa a22 4500 445851600 CHVBK 20180317145415.0 cr unu---uuuuu 170323e20111201xx s 000 0 eng 10.1007/s11227-011-0594-4 doi (NATIONALLICENCE)springer-10.1007/s11227-011-0594-4 Adaptive parallel interval branch and bound algorithms based on their performance for multicore architectures [Elektronische Daten] [J. Sanjuan-Estrada, L. Casado, I. García] This work studies how to adapt the number of threads of a parallel Interval Branch and Bound algorithm to the available computational resources based on its current performance. Basically, a thread can create a new thread that will process part of the ancestor workload. In this way, load balancing is inherent to the creation of threads. The applications in which we are interested use branch-and-bound algorithms which are highly irregular and therefore difficult to predict. The proposed methods can be used for more predictable algorithms as well. This research complements and does not substitute other devices that improve the exploitation of the system, such as dynamic scheduling policies or work-stealing. Several approaches are presented. They differ in the metrics used and in the need or not having to modify the Operating System (O.S.). The scenario for this research is just one multithreaded application running in a multicore architecture. Experimental results show that the appropriate number of running threads can be determined at run-time, avoiding having to statically establish the number of threads of an application. Thread creation decisions have to be made frequently to obtain better results, but are time-consuming. One of the presented models uses the existence of an idle processor to carry out these decisions, obtaining the desired results. Springer Science+Business Media, LLC, 2011 Multithreaded nationallicence Shared memory parallel processors nationallicence Performance analysis nationallicence Branch-and-bound nationallicence Global optimization nationallicence Irregularity nationallicence Sanjuan-Estrada J. Department of Computer Architecture and Electronics, University of Almeria, Almeria, Spain aut Casado L. Department of Computer Architecture and Electronics, University of Almeria, Almeria, Spain aut García I. Department of Computer Architecture, University of Málaga, Málaga, Spain aut The Journal of Supercomputing Springer US; http://www.springer-ny.com 58/3(2011-12-01), 376-384 0920-8542 58:3<376 2011 58 11227 https://doi.org/10.1007/s11227-011-0594-4 text/html Onlinezugriff via DOI 1 research-article jats NATIONALLICENCE 856 40 https://doi.org/10.1007/s11227-011-0594-4 text/html Onlinezugriff via DOI NATIONALLICENCE 700 1- Sanjuan-Estrada J. Department of Computer Architecture and Electronics, University of Almeria, Almeria, Spain aut NATIONALLICENCE 700 1- Casado L. Department of Computer Architecture and Electronics, University of Almeria, Almeria, Spain aut NATIONALLICENCE 700 1- García I. Department of Computer Architecture, University of Málaga, Málaga, Spain aut NATIONALLICENCE 773 0- The Journal of Supercomputing Springer US; http://www.springer-ny.com 58/3(2011-12-01), 376-384 0920-8542 58:3<376 2011 58 11227 Metadata rights reserved Springer special CC-BY-NC licence nationallicence BK010053 XK010053 XK010000 NATIONALLICENCE NATIONALLICENCE NL-springer