caa a22 4500 445852313 CHVBK 20180317145417.0 cr unu---uuuuu 170323e20110701xx s 000 0 eng 10.1007/s11227-011-0558-8 doi (NATIONALLICENCE)springer-10.1007/s11227-011-0558-8 Improving IPS by network processors [Elektronische Daten] [Pablo Cascón, Julio Ortega, Yan Luo, Eric Murray, Antonio Díaz, Ignacio Rojas] Many present applications usually require high communication throughputs. Multiprocessor nodes and multicore architectures, as well as programmable NICs (Network Interface Cards) provide new opportunities to take advantage of the available multigigabits per second link bandwidths. Nevertheless, to achieve adequate communication performance levels efficient parallel processing of network tasks and interfaces should be considered. In this paper, we leverage network processors as heterogeneous microarchitectures with several cores that implement multithreading and are suited for packet processing, to investigate on the use of parallel processing to accelerate the network interface, and thus the network applications developed above it. More specifically, we have implemented an intrusion prevention system (IPS) with such a network processor. We describe the IPS we have developed that after its offloaded implementation allows faster packet processing of both normal and corrupted traffic. The benefits from placing the IPS close to the network, by using specialized network processors, give many times lower latency and higher bandwidth available to the legitimate traffic. Springer Science+Business Media, LLC, 2011 Network processors nationallicence Offloading nationallicence IPS nationallicence Parallel network interface nationallicence Multithreading nationallicence Cascón Pablo Department of Computer Architecture and Technology, University of Granada, Granada, Spain aut Ortega Julio Department of Computer Architecture and Technology, University of Granada, Granada, Spain aut Luo Yan Department of Electrical and Computer Engineering, University of Massachusetts Lowell, Lowell, MA, USA aut Murray Eric Department of Electrical and Computer Engineering, University of Massachusetts Lowell, Lowell, MA, USA aut Díaz Antonio Department of Computer Architecture and Technology, University of Granada, Granada, Spain aut Rojas Ignacio Department of Computer Architecture and Technology, University of Granada, Granada, Spain aut The Journal of Supercomputing Springer US; http://www.springer-ny.com 57/1(2011-07-01), 99-108 0920-8542 57:1<99 2011 57 11227 https://doi.org/10.1007/s11227-011-0558-8 text/html Onlinezugriff via DOI 1 research-article jats NATIONALLICENCE 856 40 https://doi.org/10.1007/s11227-011-0558-8 text/html Onlinezugriff via DOI NATIONALLICENCE 700 1- Cascón Pablo Department of Computer Architecture and Technology, University of Granada, Granada, Spain aut NATIONALLICENCE 700 1- Ortega Julio Department of Computer Architecture and Technology, University of Granada, Granada, Spain aut NATIONALLICENCE 700 1- Luo Yan Department of Electrical and Computer Engineering, University of Massachusetts Lowell, Lowell, MA, USA aut NATIONALLICENCE 700 1- Murray Eric Department of Electrical and Computer Engineering, University of Massachusetts Lowell, Lowell, MA, USA aut NATIONALLICENCE 700 1- Díaz Antonio Department of Computer Architecture and Technology, University of Granada, Granada, Spain aut NATIONALLICENCE 700 1- Rojas Ignacio Department of Computer Architecture and Technology, University of Granada, Granada, Spain aut NATIONALLICENCE 773 0- The Journal of Supercomputing Springer US; http://www.springer-ny.com 57/1(2011-07-01), 99-108 0920-8542 57:1<99 2011 57 11227 Metadata rights reserved Springer special CC-BY-NC licence nationallicence BK010053 XK010053 XK010000 NATIONALLICENCE NATIONALLICENCE NL-springer