caa a22 4500 445852410 CHVBK 20180317145417.0 cr unu---uuuuu 170323e20110901xx s 000 0 eng 10.1007/s11227-010-0409-z doi (NATIONALLICENCE)springer-10.1007/s11227-010-0409-z Natural instruction level parallelism-aware compiler forhigh-performance QueueCore processor architecture [Elektronische Daten] [Ben Abderazek, Masashi Masuda, Arquimedes Canedo, Kenichi Kuroda] This work presents a static method implemented in a compiler for extracting high instruction level parallelism for the 32-bit QueueCore, a queue computation-based processor. The instructions of a queue processor implicitly read and write their operands, making instructions short and the programs free of false dependencies. This characteristic allows the exploitation of maximum parallelism and improves code density. Compiling for the QueueCore requires a new approach since the concept of registers disappears. We propose a new efficient code generation algorithm for the QueueCore. For a set of numerical benchmark programs, our compiler extracts more parallelism than the optimizing compiler for an RISC machine by a factor of 1.38. Through the use of QueueCore's reduced instruction set, we are able to generate 20% and 26% denser code than two embedded RISC processors. Springer Science+Business Media, LLC, 2010 Instruction level parallelism nationallicence Compiler nationallicence Queue processor nationallicence High-performance nationallicence Abderazek Ben School of Computer Science and Engineering, Adaptive Systems Laboratory, The University of Aizu, 965-8580, Aizu-Wakamatsu-shi, Fukushima-ken, Japan aut Masuda Masashi School of Computer Science and Engineering, Adaptive Systems Laboratory, The University of Aizu, 965-8580, Aizu-Wakamatsu-shi, Fukushima-ken, Japan aut Canedo Arquimedes School of Computer Science and Engineering, Adaptive Systems Laboratory, The University of Aizu, 965-8580, Aizu-Wakamatsu-shi, Fukushima-ken, Japan aut Kuroda Kenichi School of Computer Science and Engineering, Adaptive Systems Laboratory, The University of Aizu, 965-8580, Aizu-Wakamatsu-shi, Fukushima-ken, Japan aut The Journal of Supercomputing Springer US; http://www.springer-ny.com 57/3(2011-09-01), 314-338 0920-8542 57:3<314 2011 57 11227 https://doi.org/10.1007/s11227-010-0409-z text/html Onlinezugriff via DOI 1 research-article jats NATIONALLICENCE 856 40 https://doi.org/10.1007/s11227-010-0409-z text/html Onlinezugriff via DOI NATIONALLICENCE 700 1- Abderazek Ben School of Computer Science and Engineering, Adaptive Systems Laboratory, The University of Aizu, 965-8580, Aizu-Wakamatsu-shi, Fukushima-ken, Japan aut NATIONALLICENCE 700 1- Masuda Masashi School of Computer Science and Engineering, Adaptive Systems Laboratory, The University of Aizu, 965-8580, Aizu-Wakamatsu-shi, Fukushima-ken, Japan aut NATIONALLICENCE 700 1- Canedo Arquimedes School of Computer Science and Engineering, Adaptive Systems Laboratory, The University of Aizu, 965-8580, Aizu-Wakamatsu-shi, Fukushima-ken, Japan aut NATIONALLICENCE 700 1- Kuroda Kenichi School of Computer Science and Engineering, Adaptive Systems Laboratory, The University of Aizu, 965-8580, Aizu-Wakamatsu-shi, Fukushima-ken, Japan aut NATIONALLICENCE 773 0- The Journal of Supercomputing Springer US; http://www.springer-ny.com 57/3(2011-09-01), 314-338 0920-8542 57:3<314 2011 57 11227 Metadata rights reserved Springer special CC-BY-NC licence nationallicence BK010053 XK010053 XK010000 NATIONALLICENCE NATIONALLICENCE NL-springer