caa a22 4500 465742432 CHVBK 20180323111811.0 cr unu---uuuuu 170327e19901001xx s 000 0 eng 10.1007/BF00935001 doi (NATIONALLICENCE)springer-10.1007/BF00935001 Swartzlander Jr. Earl The University of Texas at Austin, Austin, Texas aut Generic signal processor implementation with VHSIC [Elektronische Daten] [Earl Swartzlander Jr.] This paper illustrates the relationship between clock and data rates for a variety of generic processor architectures. A significant result for signal processing is that if memory and arithmetic chips operate at the same clock rate, processor performance is constrained by the rate at which memory may be accessed. The paper presents a case study of the implementation of a typical generic signal processor, the AOSP Macro Function Signal Processor using Very High Speed Integrated Circuit (VHSIC) technology. It is shown that VHSIC technology, with high speeds and high levels of integration is well suited to the implementation of this generic signal processor. Kluwer Academic Publishers, 1990 Journal of VLSI Signal Processing Springer Netherlands 2/2(1990-10-01), 111-116 0922-5773 2:2<111 1990 2 11265 https://doi.org/10.1007/BF00935001 text/html Onlinezugriff via DOI 1 research-article jats NATIONALLICENCE 856 40 https://doi.org/10.1007/BF00935001 text/html Onlinezugriff via DOI NATIONALLICENCE 100 1- Swartzlander Jr Earl The University of Texas at Austin, Austin, Texas aut NATIONALLICENCE 773 0- Journal of VLSI Signal Processing Springer Netherlands 2/2(1990-10-01), 111-116 0922-5773 2:2<111 1990 2 11265 Metadata rights reserved Springer special CC-BY-NC licence nationallicence BK010053 XK010053 XK010000 NATIONALLICENCE NATIONALLICENCE NL-springer