caa a22 4500 467921415 CHVBK 20180406152918.0 cr unu---uuuuu 170328e20060601xx s 000 0 eng 10.1007/s10836-006-8950-7 doi (NATIONALLICENCE)springer-10.1007/s10836-006-8950-7 Seuring Markus AMD Saxony, Dresden Design Center, 01109, Dresden, Germany aut Combining Scan Test and Built-in Self Test [Elektronische Daten] [Markus Seuring] For digital chips containing functional logic and embedded memories, these are usually tested separately: Scan test is used for testing functional logic; Memory Built-in Self Test (MBIST) is run for embedded memories. A new approach is proposed to exercise scan test and MBIST in parallel in order to reduce production test time and improve stress tests. It requires only small additional logic and allows to simultaneously run both test modes. In general, the approach can be used to control simultaneously scan test and any Built-in Self Test (BIST) providing a simple pass/fail result. Springer Science + Business Media, LLC, 2006 scan test nationallicence BIST nationallicence MBIST nationallicence production test nationallicence stress test nationallicence Journal of Electronic Testing Kluwer Academic Publishers 22/3(2006-06-01), 297-299 0923-8174 22:3<297 2006 22 10836 https://doi.org/10.1007/s10836-006-8950-7 text/html Onlinezugriff via DOI 1 research-article jats NATIONALLICENCE 856 40 https://doi.org/10.1007/s10836-006-8950-7 text/html Onlinezugriff via DOI NATIONALLICENCE 100 1- Seuring Markus AMD Saxony, Dresden Design Center, 01109, Dresden, Germany aut NATIONALLICENCE 773 0- Journal of Electronic Testing Kluwer Academic Publishers 22/3(2006-06-01), 297-299 0923-8174 22:3<297 2006 22 10836 Metadata rights reserved Springer special CC-BY-NC licence nationallicence BK010053 XK010053 XK010000 NATIONALLICENCE NATIONALLICENCE NL-springer