caa a22 4500 467921571 CHVBK 20180406152918.0 cr unu---uuuuu 170328e20061201xx s 000 0 eng 10.1007/s10836-006-9444-3 doi (NATIONALLICENCE)springer-10.1007/s10836-006-9444-3 Huang Jiun-Lang Graduate Institute of Electronics Engineering/Department of Electrical Engineering, National Taiwan University, No. 1, Sec. 4, Roosevelt Rd., 106, Taipei, Taiwan aut On-Chip Random Jitter Testing Using Low Tap-Count Coarse Delay Lines [Elektronische Daten] [Jiun-Lang Huang] An on-chip RMS jitter testing technique for design-for-test (DfT) applications is presented in this paper. In addition to utilizing a less complicated low tap-count variable delay line to sample the jitter's cumulative density function (CDF), a sophisticated post-processing algorithm is developed to enhance process variation tolerance. Our simulation results show that using an eight-tap delay line, the probability of making correct pass/fail decisions is higher than 99% in the presence of up to 30% delay line value deviations. Springer Science + Business Media, LLC, 2006 jitter measurement nationallicence random jitter nationallicence design-for-test nationallicence analog/mixed-signal testing nationallicence Journal of Electronic Testing Kluwer Academic Publishers 22/4-6(2006-12-01), 387-398 0923-8174 22:4-6<387 2006 22 10836 https://doi.org/10.1007/s10836-006-9444-3 text/html Onlinezugriff via DOI 1 research-article jats NATIONALLICENCE 856 40 https://doi.org/10.1007/s10836-006-9444-3 text/html Onlinezugriff via DOI NATIONALLICENCE 100 1- Huang Jiun-Lang Graduate Institute of Electronics Engineering/Department of Electrical Engineering, National Taiwan University, No. 1, Sec. 4, Roosevelt Rd., 106, Taipei, Taiwan aut NATIONALLICENCE 773 0- Journal of Electronic Testing Kluwer Academic Publishers 22/4-6(2006-12-01), 387-398 0923-8174 22:4-6<387 2006 22 10836 Metadata rights reserved Springer special CC-BY-NC licence nationallicence BK010053 XK010053 XK010000 NATIONALLICENCE NATIONALLICENCE NL-springer