caa a22 4500 467921687 CHVBK 20180406152918.0 cr unu---uuuuu 170328e20060401xx s 000 0 eng 10.1007/s10836-005-4631-1 doi (NATIONALLICENCE)springer-10.1007/s10836-005-4631-1 An Efficient BIST Architecture for Delay Faults in the Logic Cells of Symmetrical SRAM-Based FPGAs [Elektronische Daten] [Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell] The objective of this paper is to propose a BIST scheme enabling the test of delay faults in all the Look-Up Tables (LUTs) of FPGA SRAMs, in a Manufacturing context. The BIST scheme does not consume any area overhead and can be removed from the device after the test thus, allowing the use of the whole circuit by the user. The structure we propose is composed of a simple test pattern generator, an error detector and a chain of LUTs. The chain of LUTs is formed alternatively by a LUT and a flip-flop. By using such a chain, the test of all delay faults in every LUT is enabled. In this paper, we develop an experiment based on the implantation of our BIST architecture in a Virtex FPGA from Xilinx. The purpose of this experiment is to show the feasibility of our solution. As a result, one important issue from this solution is its ability to detect the "smallest” delay faults in the LUTs, i.e. the smallest delays that can be observed on a LUT output. Springer Science + Business Media, LLC, 2006 BIST nationallicence delay faults nationallicence look-up table nationallicence Girard Patrick Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier, Université Montpellier II/CNRS (UMR 5506), Montpellier, France aut Héron Olivier Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier, Université Montpellier II/CNRS (UMR 5506), Montpellier, France aut Pravossoudovitch Serge Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier, Université Montpellier II/CNRS (UMR 5506), Montpellier, France aut Renovell Michel Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier, Université Montpellier II/CNRS (UMR 5506), Montpellier, France aut Journal of Electronic Testing Kluwer Academic Publishers 22/2(2006-04-01), 161-172 0923-8174 22:2<161 2006 22 10836 https://doi.org/10.1007/s10836-005-4631-1 text/html Onlinezugriff via DOI 1 research-article jats NATIONALLICENCE 856 40 https://doi.org/10.1007/s10836-005-4631-1 text/html Onlinezugriff via DOI NATIONALLICENCE 700 1- Girard Patrick Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier, Université Montpellier II/CNRS (UMR 5506), Montpellier, France aut NATIONALLICENCE 700 1- Héron Olivier Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier, Université Montpellier II/CNRS (UMR 5506), Montpellier, France aut NATIONALLICENCE 700 1- Pravossoudovitch Serge Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier, Université Montpellier II/CNRS (UMR 5506), Montpellier, France aut NATIONALLICENCE 700 1- Renovell Michel Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier, Université Montpellier II/CNRS (UMR 5506), Montpellier, France aut NATIONALLICENCE 773 0- Journal of Electronic Testing Kluwer Academic Publishers 22/2(2006-04-01), 161-172 0923-8174 22:2<161 2006 22 10836 Metadata rights reserved Springer special CC-BY-NC licence nationallicence BK010053 XK010053 XK010000 NATIONALLICENCE NATIONALLICENCE NL-springer