caa a22 4500 469039752 CHVBK 20180323132807.0 cr unu---uuuuu 170328e19920201xx s 000 0 eng 10.1007/BF00159830 doi (NATIONALLICENCE)springer-10.1007/BF00159830 Parity bit calculation and test signal compaction for BIST applications [Elektronische Daten] [Sungju Park, Sheldon Akers] Parity bit checking and pseudo-exhaustive testing are two design techniques which have been widely discussed in the BIST literature but have seldom been employed in practice because of the exponential nature of the processes involved. In this paper we describe several procedures designed to avoid these exponential explosions. Specifically we show how the parity of a large combinational function can (often) be quickly calculated. This is accomplished by an examination of the circuit realization itself particularly with regard to the connectivity between the various inputs and outputs. We then show how this same approach can be used to partition circuits so that they can be tested efficiently with a relatively small number of test patterns. Using these methods we were able to calculate the parity bits for more than 80% of ISCAS benchmark circuits' outputs. Interestingly enough, only 15% of these outputs were found to be parity-odd, but for these cases high fault coverage was invariably found to result. Several examples are included. Kluwer Academic Publishers, 1992 Built-in self-test nationallicence parity bit nationallicence pseudo-exhaustive tests nationallicence test response compression nationallicence Park Sungju Department of Electrical and Computer Engineering, University of Massachusetts, 01003, Amherst, MA, USA aut Akers Sheldon Department of Electrical and Computer Engineering, University of Massachusetts, 01003, Amherst, MA, USA aut Journal of Electronic Testing Kluwer Academic Publishers 3/1(1992-02-01), 45-52 0923-8174 3:1<45 1992 3 10836 https://doi.org/10.1007/BF00159830 text/html Onlinezugriff via DOI 1 research-article jats NATIONALLICENCE 856 40 https://doi.org/10.1007/BF00159830 text/html Onlinezugriff via DOI NATIONALLICENCE 700 1- Park Sungju Department of Electrical and Computer Engineering, University of Massachusetts, 01003, Amherst, MA, USA aut NATIONALLICENCE 700 1- Akers Sheldon Department of Electrical and Computer Engineering, University of Massachusetts, 01003, Amherst, MA, USA aut NATIONALLICENCE 773 0- Journal of Electronic Testing Kluwer Academic Publishers 3/1(1992-02-01), 45-52 0923-8174 3:1<45 1992 3 10836 Metadata rights reserved Springer special CC-BY-NC licence nationallicence BK010053 XK010053 XK010000 NATIONALLICENCE NATIONALLICENCE NL-springer