caa a22 4500 469039906 CHVBK 20180323132808.0 cr unu---uuuuu 170328e19921201xx s 000 0 eng 10.1007/BF00135337 doi (NATIONALLICENCE)springer-10.1007/BF00135337 Quiescent current analysis and experimentation of defective CMOS circuits [Elektronische Daten] [J. Segura, V. Champac, R. Rodríguez-Montañés, J. Figueras, J. Rubio] Physical defects widely encountered in today's CMOS processes (bridges, gate oxide short (gas) and floating gates) are modeled taking into account the topology of the defective circuit and the parameters of the technology. These models are used to simulate at electrical level the behavior of a simple 3-inverter chain with a defective inverter. The results are compared with experimental data of integrated circuits fabricated with intentional defects. The influence of the characteristics of each defect on I DDQ has been investigated by electrical simulation and experimentation. Kluwer Academic Publishers, 1992 Bridging failures nationallicence current testing nationallicence defect modeling nationallicence floating gate opens nationallicence gate oxide shorts nationallicence intentionally designed defective circuits defects nationallicence Segura J. Department of Electronic Engineering, Polytechnical University of Catalonia, Diagonal 649, 08028, Barcelona, Spain aut Champac V. Department of Electronic Engineering, Polytechnical University of Catalonia, Diagonal 649, 08028, Barcelona, Spain aut Rodríguez-Montañés R. Department of Electronic Engineering, Polytechnical University of Catalonia, Diagonal 649, 08028, Barcelona, Spain aut Figueras J. Department of Electronic Engineering, Polytechnical University of Catalonia, Diagonal 649, 08028, Barcelona, Spain aut Rubio J. Department of Electronic Engineering, Polytechnical University of Catalonia, Diagonal 649, 08028, Barcelona, Spain aut Journal of Electronic Testing Kluwer Academic Publishers 3/4(1992-12-01), 337-348 0923-8174 3:4<337 1992 3 10836 https://doi.org/10.1007/BF00135337 text/html Onlinezugriff via DOI 1 research-article jats NATIONALLICENCE 856 40 https://doi.org/10.1007/BF00135337 text/html Onlinezugriff via DOI NATIONALLICENCE 700 1- Segura J. Department of Electronic Engineering, Polytechnical University of Catalonia, Diagonal 649, 08028, Barcelona, Spain aut NATIONALLICENCE 700 1- Champac V. Department of Electronic Engineering, Polytechnical University of Catalonia, Diagonal 649, 08028, Barcelona, Spain aut NATIONALLICENCE 700 1- Rodríguez-Montañés R. Department of Electronic Engineering, Polytechnical University of Catalonia, Diagonal 649, 08028, Barcelona, Spain aut NATIONALLICENCE 700 1- Figueras J. Department of Electronic Engineering, Polytechnical University of Catalonia, Diagonal 649, 08028, Barcelona, Spain aut NATIONALLICENCE 700 1- Rubio J. Department of Electronic Engineering, Polytechnical University of Catalonia, Diagonal 649, 08028, Barcelona, Spain aut NATIONALLICENCE 773 0- Journal of Electronic Testing Kluwer Academic Publishers 3/4(1992-12-01), 337-348 0923-8174 3:4<337 1992 3 10836 Metadata rights reserved Springer special CC-BY-NC licence nationallicence BK010053 XK010053 XK010000 NATIONALLICENCE NATIONALLICENCE NL-springer