caa a22 4500 469040041 CHVBK 20180323132808.0 cr unu---uuuuu 170328e19920501xx s 000 0 eng 10.1007/BF00137250 doi (NATIONALLICENCE)springer-10.1007/BF00137250 A test methodology for finite state machines using partial scan design [Elektronische Daten] [Hyoung Min, William Rogers] This paper presents an efficient automatic test pattern generation technique for loop-free circuits. A partial scan technique is used to convert a sequential circuit (finite state machine) with arbitrary feedback paths into a pipelined circuit for testing. Test generation for these modified circuits can be performed with a modified combinational automatic test pattern generator (ATPG), which is much faster than a sequential ATPG. A combinational model is obtained by replacing all flipflops by buffers. It is shown that a test vector for a fault in this model obtained by a combinational test generator can be expanded into a sequence of identical vectors to detect the same fault in the original sequential circuit. This technique may abort a few faults which can then be resolved with a sequential ATPG. Experiments on the ISCAS89 circuits show that only 30% to 70% of flipflops require scanning in larger circuits and 96% to 100% fault coverage for almost all the circuits without resorting to a sequential ATPG. Kluwer Academic Publishers, 1992 ATPG nationallicence fault nationallicence partial scan nationallicence loop-free circuits nationallicence test generation nationallicence Min Hyoung Department of Electrical and Computer Engineering, Cheon-Cheon-Dong 300, Su Win City, Kyungki-do, Korea aut Rogers William Department of Electrical and Computer Engineering, Computer Enginering Research Center, University of Texas, 78758, Austin, TX, USA aut Journal of Electronic Testing Kluwer Academic Publishers 3/2(1992-05-01), 127-137 0923-8174 3:2<127 1992 3 10836 https://doi.org/10.1007/BF00137250 text/html Onlinezugriff via DOI 1 research-article jats NATIONALLICENCE 856 40 https://doi.org/10.1007/BF00137250 text/html Onlinezugriff via DOI NATIONALLICENCE 700 1- Min Hyoung Department of Electrical and Computer Engineering, Cheon-Cheon-Dong 300, Su Win City, Kyungki-do, Korea aut NATIONALLICENCE 700 1- Rogers William Department of Electrical and Computer Engineering, Computer Enginering Research Center, University of Texas, 78758, Austin, TX, USA aut NATIONALLICENCE 773 0- Journal of Electronic Testing Kluwer Academic Publishers 3/2(1992-05-01), 127-137 0923-8174 3:2<127 1992 3 10836 Metadata rights reserved Springer special CC-BY-NC licence nationallicence BK010053 XK010053 XK010000 NATIONALLICENCE NATIONALLICENCE NL-springer