caa a22 4500 469125667 CHVBK 20180323133150.0 cr unu---uuuuu 170328e19920501xx s 000 0 eng 10.1007/BF00925121 doi (NATIONALLICENCE)springer-10.1007/BF00925121 High-speed VLSI arithmetic processor architectures using hybrid number representation [Elektronische Daten] [H. Srinivas, Keshab Parhi] This paper addresses design of high speed architectures for fixed-point, two's-complement, bit-parallel division, square-root, and multiplication operations. These architectures make use of hybrid number representations (i.e. the input and output numbers are represented using two's complement representation, and the internal numbers are represented using radix-2 redundant representation). We propose newshifted remainder conditioning, andsign multiplexing techniques in combination with novel circuit architecture approaches to obtain efficient divider and square-root architectures. Our divider exploits full dynamic range of operands and eliminates the need for on-line or off-line conversion of the result to binary (this is because our nonrestoring division and square-root operators output binary quotient). Furthermore, since the binary input set is a subset of the redundant digit set, no binary-to-redundant number conversion is necessary at the input of the divider and square-root operators. We also present a fast, new conversion scheme for converting radix-2 redundant numbers to two's complement binary numbers, and use this to design a bit-parallel multiplier. This multiplier architecture requires fewer pipelining latches than conventional two's complement multipliers, and reduces the latency of the multiplication operation from (2W-1) to aboutW (whereW is the word-length), when pipelined at the bit-level. Kluwer Academic Publishers, 1992 Srinivas H. Department of Electrical Engineering, University of Minnesota, 55455, Minneapolis, MN aut Parhi Keshab Department of Electrical Engineering, University of Minnesota, 55455, Minneapolis, MN aut Journal of VLSI signal processing systems for signal, image and video technology Springer Netherlands 4/2-3(1992-05-01), 177-198 0922-5773 4:2-3<177 1992 4 11265 https://doi.org/10.1007/BF00925121 text/html Onlinezugriff via DOI 1 research-article jats NATIONALLICENCE 856 40 https://doi.org/10.1007/BF00925121 text/html Onlinezugriff via DOI NATIONALLICENCE 700 1- Srinivas H. Department of Electrical Engineering, University of Minnesota, 55455, Minneapolis, MN aut NATIONALLICENCE 700 1- Parhi Keshab Department of Electrical Engineering, University of Minnesota, 55455, Minneapolis, MN aut NATIONALLICENCE 773 0- Journal of VLSI signal processing systems for signal, image and video technology Springer Netherlands 4/2-3(1992-05-01), 177-198 0922-5773 4:2-3<177 1992 4 11265 Metadata rights reserved Springer special CC-BY-NC licence nationallicence BK010053 XK010053 XK010000 NATIONALLICENCE NATIONALLICENCE NL-springer