caa a22 4500 469125691 CHVBK 20180323133150.0 cr unu---uuuuu 170328e19921101xx s 000 0 eng 10.1007/BF00930642 doi (NATIONALLICENCE)springer-10.1007/BF00930642 Fault tolerance in FFT arrays: Time redundancy approaches [Elektronische Daten] [A. Antola, R. Negrini, M. Sami, N. Scarabottolo] Fault tolerance in VLSI/WSI FFT arrays acquires relevance when defects and run-time faults become significant, due to large dimensions of processors and arrays. Then, both restructuring to overcome end-of-production defects and reconfiguration to overcome run-time faults are required, to achieve the dual purposes of higher yield and higher reliability. Adopting as basic FFT network the two-dimensions array that directly corresponds to the FFT flow graph, the usual structure redundancy techniques tailored for two-dimensions arrays reconfiguration are not well applicable, since the limited locality of this network leads to relevant area increase due to the augmented interconnection structure. In this paper,time redundancy is suggested as a viable alternative for the two-dimensions FFT array; two different solutions are presented, one based oninter-stage reconfiguration, the other one adoptingintra-state reconfiguration, both allowing for survival to multiple faults with limited increase of network complexity and very small hard-core sections. As usual in many time redundancy methods, both approaches result in a processing speed equal to half the processing speed granted by an ideal, fault-free device. Reliability and survival ratios to multiple faults are evaluated for the two cases, taking into account also the area increments necessary for fault tolerance. The reliability evaluations allow for a direct comparison of the two solutions. Kluwer Academic Publishers, 1992 Antola A. Politecnico di Milano, Dipartimento di Elettronica e Informazione, Piazza Leonardo da Vinci, 32/20133, Milano, Italy aut Negrini R. Politecnico di Milano, Dipartimento di Elettronica e Informazione, Piazza Leonardo da Vinci, 32/20133, Milano, Italy aut Sami M. Politecnico di Milano, Dipartimento di Elettronica e Informazione, Piazza Leonardo da Vinci, 32/20133, Milano, Italy aut Scarabottolo N. Politecnico di Milano, Dipartimento di Elettronica e Informazione, Piazza Leonardo da Vinci, 32/20133, Milano, Italy aut Journal of VLSI signal processing systems for signal, image and video technology Springer Netherlands 4/4(1992-11-01), 295-316 0922-5773 4:4<295 1992 4 11265 https://doi.org/10.1007/BF00930642 text/html Onlinezugriff via DOI 1 research-article jats NATIONALLICENCE 856 40 https://doi.org/10.1007/BF00930642 text/html Onlinezugriff via DOI NATIONALLICENCE 700 1- Antola A. Politecnico di Milano, Dipartimento di Elettronica e Informazione, Piazza Leonardo da Vinci, 32/20133, Milano, Italy aut NATIONALLICENCE 700 1- Negrini R. Politecnico di Milano, Dipartimento di Elettronica e Informazione, Piazza Leonardo da Vinci, 32/20133, Milano, Italy aut NATIONALLICENCE 700 1- Sami M. Politecnico di Milano, Dipartimento di Elettronica e Informazione, Piazza Leonardo da Vinci, 32/20133, Milano, Italy aut NATIONALLICENCE 700 1- Scarabottolo N. Politecnico di Milano, Dipartimento di Elettronica e Informazione, Piazza Leonardo da Vinci, 32/20133, Milano, Italy aut NATIONALLICENCE 773 0- Journal of VLSI signal processing systems for signal, image and video technology Springer Netherlands 4/4(1992-11-01), 295-316 0922-5773 4:4<295 1992 4 11265 Metadata rights reserved Springer special CC-BY-NC licence nationallicence BK010053 XK010053 XK010000 NATIONALLICENCE NATIONALLICENCE NL-springer