caa a22 4500 469125764 CHVBK 20180323133150.0 cr unu---uuuuu 170328e19921101xx s 000 0 eng 10.1007/BF00930645 doi (NATIONALLICENCE)springer-10.1007/BF00930645 Multidimensional fourier transforms by systolic architectures [Elektronische Daten] [T. Roziner, M. Karpovsky] In this paper, time-efficient systolic and semi-systolic architectures for the implementation of multidimensional DFTs are proposed that allow modularity and easy expansibility while keeping throughput independent of the dimension of the DFT. We shall call an array semi-systolic if the input data is to be preloaded into every cell of the array or if the output data can be calculated not only in the boundary cells of the array. DFT algorithms are represented by FORTRAN-like code, in order to explicitly display the suggested rotational transformations in the index space. After the transformation, multidimensional DFT algorithm can be mapped onto a systolic structure. The area-time2 complexity of the proposed design is within logk factor of the lower bound for ak-point DFT (AT 2=Ω(k 2 log2 k)), i.e. equals 0(k 2 log3 k)=0(N 2M log3 N) fork=N 2M point DFT;A is the area complexity andT is the system throughput. Kluwer Academic Publishers, 1992 Roziner T. Research Laboratory for Design and Testing of Computers and Communication Systems, Department of Electrical, Computer, and Systems Engineering, Boston University, 44 Cummington Street, 02215, Boston, Massachusetts aut Karpovsky M. Research Laboratory for Design and Testing of Computers and Communication Systems, Department of Electrical, Computer, and Systems Engineering, Boston University, 44 Cummington Street, 02215, Boston, Massachusetts aut Journal of VLSI signal processing systems for signal, image and video technology Springer Netherlands 4/4(1992-11-01), 343-354 0922-5773 4:4<343 1992 4 11265 https://doi.org/10.1007/BF00930645 text/html Onlinezugriff via DOI 1 research-article jats NATIONALLICENCE 856 40 https://doi.org/10.1007/BF00930645 text/html Onlinezugriff via DOI NATIONALLICENCE 700 1- Roziner T. Research Laboratory for Design and Testing of Computers and Communication Systems, Department of Electrical, Computer, and Systems Engineering, Boston University, 44 Cummington Street, 02215, Boston, Massachusetts aut NATIONALLICENCE 700 1- Karpovsky M. Research Laboratory for Design and Testing of Computers and Communication Systems, Department of Electrical, Computer, and Systems Engineering, Boston University, 44 Cummington Street, 02215, Boston, Massachusetts aut NATIONALLICENCE 773 0- Journal of VLSI signal processing systems for signal, image and video technology Springer Netherlands 4/4(1992-11-01), 343-354 0922-5773 4:4<343 1992 4 11265 Metadata rights reserved Springer special CC-BY-NC licence nationallicence BK010053 XK010053 XK010000 NATIONALLICENCE NATIONALLICENCE NL-springer