Process optimization of polymetal (W/WN/Polysilicon) gate and its impact on dynamic random-access memory chip performance in 0.14-µm technology

Verfasser / Beitragende:
[Pil Shim, Jun-Ho Choy, Gyung Gil, Ki Kyung, Ju Park]
Ort, Verlag, Jahr:
2002
Enthalten in:
Journal of Electronic Materials, 31/10(2002-10-01), 988-993
Format:
Artikel (online)
ID: 471147966