naa a22 4500 51080537X CHVBK 20180411083415.0 cr unu---uuuuu 180411e20131101xx s 000 0 eng 10.1007/s11664-013-2773-y doi (NATIONALLICENCE)springer-10.1007/s11664-013-2773-y Design of Dislocation-Compensated ZnS y Se1− y /GaAs (001) Heterostructures [Elektronische Daten] [T. Kujofsa, J.E. Ayers] The understanding of lattice relaxation and dislocation dynamics in lattice-mismatched semiconductors makes it possible to design metamorphic device structures utilizing the dislocation compensation mechanism for reduced defects, improved performance, and enhanced reliability. We have developed a dislocation dynamics model accounting for misfit-threading interactions and have applied it to ZnS y Se1−y /GaAs (001) heterostructures.1 Dislocation compensation involves the removal of threading dislocations associated with one sense of misfit dislocations by bending them over to create misfit dislocations of the opposite sense at an intentionally mismatched interface. Here we investigated the design of dislocation-compensated ZnS y Se1−y /GaAs (001) heterostructures and considered the sulfur mole fraction tolerances applicable to such structures. We considered two types of structures: typeA involved a uniform-composition (ungraded) layer on top of a uniform-composition buffer, while typeB involved a uniform-composition layer on a linearly graded buffer. For each structure type we studied the requirements on the thickness and compositional profile of the buffer layer to optimize the removal of mobile threading dislocations from the top uniform (device) layer as well as the allowed tolerance in compositional overshoot to achieve structures with low threading dislocation density. We show for both types of structure that (i) for given compositional overshoot at the buffer-device layer interface, there is an optimum buffer thickness which minimizes the dislocation density; and (ii) for given buffer thickness there is an optimum overshoot which minimizes the dislocation density. TMS, 2013 Relaxation nationallicence dislocation compensation nationallicence linearly and ungraded buffers nationallicence compositional tolerance nationallicence Kujofsa T. Electrical and Computer Engineering Department, University of Connecticut, 371 Fairfield Way, Unit 4157, 06269-4157, Storrs, CT, USA aut Ayers J.E. Electrical and Computer Engineering Department, University of Connecticut, 371 Fairfield Way, Unit 4157, 06269-4157, Storrs, CT, USA aut Journal of Electronic Materials Springer US; http://www.springer-ny.com 42/11(2013-11-01), 3034-3040 0361-5235 42:11<3034 2013 42 11664 https://doi.org/10.1007/s11664-013-2773-y text/html Onlinezugriff via DOI 1 research-article jats NATIONALLICENCE 856 40 https://doi.org/10.1007/s11664-013-2773-y text/html Onlinezugriff via DOI NATIONALLICENCE 700 1- Kujofsa T. Electrical and Computer Engineering Department, University of Connecticut, 371 Fairfield Way, Unit 4157, 06269-4157, Storrs, CT, USA aut NATIONALLICENCE 700 1- Ayers J.E. Electrical and Computer Engineering Department, University of Connecticut, 371 Fairfield Way, Unit 4157, 06269-4157, Storrs, CT, USA aut NATIONALLICENCE 773 0- Journal of Electronic Materials Springer US; http://www.springer-ny.com 42/11(2013-11-01), 3034-3040 0361-5235 42:11<3034 2013 42 11664 Metadata rights reserved Springer special CC-BY-NC licence nationallicence BK010053 XK010053 XK010000 NATIONALLICENCE NATIONALLICENCE NL-springer