caa a22 4500 606204938 CHVBK 20210128101005.0 cr unu---uuuuu 210128e20150601xx s 000 0 eng 10.1007/s00034-014-9949-4 doi (NATIONALLICENCE)springer-10.1007/s00034-014-9949-4 A Power- and Area-Efficient Multirate Quasi-Cyclic LDPC Decoder [Elektronische Daten] [Michaelraj Roberts, Ramesh Jayabalan] In this paper, a power- and area-efficient, multirate, Quasi-cyclic, low-density, parity-check decoder is proposed. The proposed decoder design is based on a simplified adaptive normalized min-sum algorithm. The proposed algorithm effectively utilizes two correction factors for check-node and variable-node update processes. This corrects the channel errors at relatively low signal-to-noise ratio. In order to reduce the finite word length effects, a six-bit nonuniform quantization with the overlapped message passing scheme is used. In addition, an improved early termination scheme is also used to reduce the total number of decoding iterations. This reduces the overall power consumption of the decoder. The simulations have been carried out using Xilinx ISE 14.1 and implemented on Virtex 5 FPGA. The proposed decoder is synthesized using CADENCE with UMC 130 nm technology. With a core area of 1.16 mm $$^{2}$$ 2 , the proposed decoder achieves a maximum throughput of 3.4 Gb/s for 15 decoding iterations with a power dissipation of 114.3 mW. Springer Science+Business Media New York, 2014 Iterative decoding nationallicence Early termination scheme nationallicence Low-density parity-check (LDPC) codes nationallicence Nonuniform quantization nationallicence Multirate nationallicence Quasi-Cyclic LDPC (QC-LDPC) codes nationallicence Roberts Michaelraj Department of Electronics and Communication Engineering, PSG College of Technology, Peelamedu Post, 641004, Coimbatore, Tamil Nadu, India aut Jayabalan Ramesh Department of Electronics and Communication Engineering, PSG College of Technology, Peelamedu Post, 641004, Coimbatore, Tamil Nadu, India aut Circuits, Systems, and Signal Processing Springer US; http://www.springer-ny.com 34/6(2015-06-01), 2015-2035 0278-081X 34:6<2015 2015 34 34 https://doi.org/10.1007/s00034-014-9949-4 text/html Onlinezugriff via DOI BK010053 XK010053 XK010000 Metadata rights reserved Springer special CC-BY-NC licence nationallicence 1 research-article jats NATIONALLICENCE NATIONALLICENCE NL-springer NATIONALLICENCE 856 40 https://doi.org/10.1007/s00034-014-9949-4 text/html Onlinezugriff via DOI NATIONALLICENCE 700 1- Roberts Michaelraj Department of Electronics and Communication Engineering, PSG College of Technology, Peelamedu Post, 641004, Coimbatore, Tamil Nadu, India aut NATIONALLICENCE 700 1- Jayabalan Ramesh Department of Electronics and Communication Engineering, PSG College of Technology, Peelamedu Post, 641004, Coimbatore, Tamil Nadu, India aut NATIONALLICENCE 773 0- Circuits, Systems, and Signal Processing Springer US; http://www.springer-ny.com 34/6(2015-06-01), 2015-2035 0278-081X 34:6<2015 2015 34 34