caa a22 4500 606205012 CHVBK 20210128101005.0 cr unu---uuuuu 210128e20150601xx s 000 0 eng 10.1007/s00034-014-9933-z doi (NATIONALLICENCE)springer-10.1007/s00034-014-9933-z Pastuszak Grzegorz Institute of Radioelectronics, Warsaw University of Technology, Nowowiejska 15/19, 00-665, Warsaw, Poland aut Flexible Architecture Design for H.265/HEVC Inverse Transform [Elektronische Daten] [Grzegorz Pastuszak] Highly-efficient video coding involves a great amount of computations. Hardware encoders apply different parallelization techniques to satisfy real-time requirements. This paper describes a novel design methodology for the 2D inverse transform used in the H.265/HEVC hardware decoder and encoder. To support different transform sizes, matrix multiplications are decomposed into some steps based on the division of transform blocks into fixed-size subblocks. The assumed order of processed subblocks along with separate transform cores assigned to both dimensions allows a significant reduction of the size of the transposition buffer, which in turn decreases the resource consumption of the whole architecture. The decomposition enables different hardware configurations of the architectures. Particularly, configuration parameters enable the tradeoff between resources and throughput, the interface adaptation to desired horizontal and vertical sizes, and the availability of particular transform sizes. Two versions of the architecture are developed for FPGA and ASIC technologies. Synthesis results show that they can operate at 200 and 400MHz when implemented in FPGA Arria II and TSMC 90nm, respectively. The Author(s), 2014 H.265/HEVC nationallicence Video coding nationallicence Discrete cosine transform (DCT) nationallicence FPGA nationallicence VLSI nationallicence Circuits, Systems, and Signal Processing Springer US; http://www.springer-ny.com 34/6(2015-06-01), 1931-1945 0278-081X 34:6<1931 2015 34 34 https://doi.org/10.1007/s00034-014-9933-z text/html Onlinezugriff via DOI BK010053 XK010053 XK010000 Metadata rights reserved Springer special CC-BY-NC licence nationallicence 1 research-article jats NATIONALLICENCE NATIONALLICENCE NL-springer NATIONALLICENCE 856 40 https://doi.org/10.1007/s00034-014-9933-z text/html Onlinezugriff via DOI NATIONALLICENCE 100 1- Pastuszak Grzegorz Institute of Radioelectronics, Warsaw University of Technology, Nowowiejska 15/19, 00-665, Warsaw, Poland aut NATIONALLICENCE 773 0- Circuits, Systems, and Signal Processing Springer US; http://www.springer-ny.com 34/6(2015-06-01), 1931-1945 0278-081X 34:6<1931 2015 34 34