caa a22 4500 606205551 CHVBK 20210128101007.0 cr unu---uuuuu 210128e20151201xx s 000 0 eng 10.1007/s00034-015-0045-1 doi (NATIONALLICENCE)springer-10.1007/s00034-015-0045-1 Performance Analysis of a Modified MAP Decoder Architecture for Low Power Dissipation [Elektronische Daten] [S. Shiyamala, V. Rajamani] A modified architecture for minimized power dissipation in the maximum a posteriori (MAP) decoder based on clock gating and toggle filtering is proposed in this paper. Log likelihood ratio (LLR) in the trellis structure of the MAP decoder consumes large power. To minimize the power dissipation, toggle-filtering technique is introduced in the LLR unit of MAP decoder and clock-gating approach is introduced in the state metric, branch metric and again in LLR blocks of the MAP decoder. Toggle filter is used to avoid early injection of signals from the state metric and branch metric units. Clock-gating approach is used to keep the idle block in the disabled state. A power dissipation of 53.64% has been achieved when toggle-filtering technique is applied and 54.4% when clock-gating technique is applied. Power dissipation of 64.07% has been achieved for the combined effect of toggle-filtering and clock-gating technique. Springer Science+Business Media New York, 2015 Decoder nationallicence Folded technique nationallicence Clock gating nationallicence Toggle filter nationallicence Power dissipation nationallicence Shiyamala S. Department of Electronics and Communication Engineering, SBM College of Engineering and Technology, Dindigul, TN, India aut Rajamani V. Department of Electronics and Communication Engineering, Veltech Multitech Dr. Rangarajan Dr. Sakunthala Engineering College, Chennai, TN, India aut Circuits, Systems, and Signal Processing Springer US; http://www.springer-ny.com 34/12(2015-12-01), 3949-3964 0278-081X 34:12<3949 2015 34 34 https://doi.org/10.1007/s00034-015-0045-1 text/html Onlinezugriff via DOI BK010053 XK010053 XK010000 Metadata rights reserved Springer special CC-BY-NC licence nationallicence 1 research-article jats NATIONALLICENCE NATIONALLICENCE NL-springer NATIONALLICENCE 856 40 https://doi.org/10.1007/s00034-015-0045-1 text/html Onlinezugriff via DOI NATIONALLICENCE 700 1- Shiyamala S. Department of Electronics and Communication Engineering, SBM College of Engineering and Technology, Dindigul, TN, India aut NATIONALLICENCE 700 1- Rajamani V. Department of Electronics and Communication Engineering, Veltech Multitech Dr. Rangarajan Dr. Sakunthala Engineering College, Chennai, TN, India aut NATIONALLICENCE 773 0- Circuits, Systems, and Signal Processing Springer US; http://www.springer-ny.com 34/12(2015-12-01), 3949-3964 0278-081X 34:12<3949 2015 34 34