caa a22 4500 606205578 CHVBK 20210128101007.0 cr unu---uuuuu 210128e20150301xx s 000 0 eng 10.1007/s00034-014-9887-1 doi (NATIONALLICENCE)springer-10.1007/s00034-014-9887-1 A Symmetric, Multi-Threshold, High-Speed and Efficient-Energy 1-Bit Full Adder Cell Design Using CNFET Technology [Elektronische Daten] [Yavar SafaeiMehrabani, Mohammad Eshghi] This paper presents two asymmetric and symmetric multi-threshold, high-speed, and energy-efficient Full Adder cells using Carbon Nanotube Field Effect Transistors (CNFETs). The utilization of unique properties to CNFETs to build structures inaccessible to MOSFETs technology is also evoked, particularly due to geometry-dependent threshold voltages ( $$V_\mathrm{{th}} )$$ V th ) in multiple- $$V_\mathrm{{th}} $$ V th designs to achieve high-performance circuits. In order to evaluate the proposed designs, computer simulations are carried out using 32 nm-CMOS and 32 nm-CNFET technologies. Comprehensive experiments are performed to evaluate the performance of the proposed designs using different low voltage power supplies, load capacitors, frequencies, and temperatures. Simulation results demonstrate the superiority of the proposed designs in terms of delay and power-delay product compared to the other classical and state-of-the-art CMOS and CNFET-based Full Adder cells. Moreover, in order to evaluate the robustness of the proposed symmetric cell against the variations and mismatches of both diameter of the CNTs and capacitance of input capacitors, Monte Carlo transient analysis has been carried out. Simulation results confirm that the proposed cell is robust against the mentioned fluctuations. Springer Science+Business Media New York, 2015 Carbon nanotube field effect transistor (CNFET) nationallicence High-performance nationallicence Multi-threshold nationallicence Nanoelectronics nationallicence Symmetric full adder nationallicence SafaeiMehrabani Yavar Department of Computer Engineering, Science and Research Branch, Islamic Azad University, Tehran, Iran aut Eshghi Mohammad Faculty of Electrical and Computer Engineering, Shahid Beheshti University, G.C., Tehran, Iran aut Circuits, Systems, and Signal Processing Springer US; http://www.springer-ny.com 34/3(2015-03-01), 739-759 0278-081X 34:3<739 2015 34 34 https://doi.org/10.1007/s00034-014-9887-1 text/html Onlinezugriff via DOI BK010053 XK010053 XK010000 Metadata rights reserved Springer special CC-BY-NC licence nationallicence 1 research-article jats NATIONALLICENCE NATIONALLICENCE NL-springer NATIONALLICENCE 856 40 https://doi.org/10.1007/s00034-014-9887-1 text/html Onlinezugriff via DOI NATIONALLICENCE 700 1- SafaeiMehrabani Yavar Department of Computer Engineering, Science and Research Branch, Islamic Azad University, Tehran, Iran aut NATIONALLICENCE 700 1- Eshghi Mohammad Faculty of Electrical and Computer Engineering, Shahid Beheshti University, G.C., Tehran, Iran aut NATIONALLICENCE 773 0- Circuits, Systems, and Signal Processing Springer US; http://www.springer-ny.com 34/3(2015-03-01), 739-759 0278-081X 34:3<739 2015 34 34