caa a22 4500 606206280 CHVBK 20210128101010.0 cr unu---uuuuu 210128e20150501xx s 000 0 eng 10.1007/s00034-014-9908-0 doi (NATIONALLICENCE)springer-10.1007/s00034-014-9908-0 Thanachayanont Apinunt Faculty of Engineering, King Mongkut's Institute of Technology Ladkrabang, Chalongkrung road, Ladkrabang, 10520, Bangkok, Thailand aut A 1-V, 330-nW, 6-Bit Current-Mode Logarithmic Cyclic ADC for ISFET-Based $$p\!H$$ p H Digital Readout System [Elektronische Daten] [Apinunt Thanachayanont] This paper describes the design and implementation of a low-power current-mode logarithmic analog-to-digital converter (ADC) for an ISFET-based $$p\!H$$ p H digital readout system. The system comprises a front-end ISFET-based $$p\!H$$ p H readout circuit and a succeeding logarithmic ADC to produce a digital output signal which is linearly related to the input $$p\!H$$ p H variation. The front-end $$p\!H$$ p H readout circuit is realized using a subthreshold ISFET/REFET differential pair with a current-mode translinear multiplier/divider circuit. The logarithmic ADC is realized using the cyclic architecture and current-mode circuit techniques to achieve low power dissipation. High-accuracy current sample-and-hold circuit based on the regulated-cascode switched-current memory cell and low-power high-resolution current comparator are proposed for the ADC realization. All circuits were designed to operate with a single 1-V power supply voltage, and were simulated with process parameters from a 0.18- $$\mu $$ μ m CMOS technology. The power dissipation of the front-end $$p\!H$$ p H readout circuit and the logarithmic ADC is 20 and 330 nW, respectively. The front-end $$p\!H$$ p H readout circuit can produce an output current range of 0.1-300 nA which is logarithmically corresponded to the input $$p\!H$$ p H range of 4-10. The logarithmic ADC operates with 1-kS/s sampling rate and achieves the integral nonlinearity error of $$\pm 0.8$$ ± 0.8 LSB, the effective number of bits of 5.95, and 37.6-dB of signal-to-noise-distortion ratio with 100-nA full-scale input range. Springer Science+Business Media New York, 2014 Ion-sensitive FET nationallicence Logarithmic ADC nationallicence Subthreshold nationallicence Cyclic ADC nationallicence $$p\!H$$ p H readout circuit nationallicence Circuits, Systems, and Signal Processing Springer US; http://www.springer-ny.com 34/5(2015-05-01), 1405-1429 0278-081X 34:5<1405 2015 34 34 https://doi.org/10.1007/s00034-014-9908-0 text/html Onlinezugriff via DOI BK010053 XK010053 XK010000 Metadata rights reserved Springer special CC-BY-NC licence nationallicence 1 research-article jats NATIONALLICENCE NATIONALLICENCE NL-springer NATIONALLICENCE 856 40 https://doi.org/10.1007/s00034-014-9908-0 text/html Onlinezugriff via DOI NATIONALLICENCE 100 1- Thanachayanont Apinunt Faculty of Engineering, King Mongkut's Institute of Technology Ladkrabang, Chalongkrung road, Ladkrabang, 10520, Bangkok, Thailand aut NATIONALLICENCE 773 0- Circuits, Systems, and Signal Processing Springer US; http://www.springer-ny.com 34/5(2015-05-01), 1405-1429 0278-081X 34:5<1405 2015 34 34