caa a22 4500 606206299 CHVBK 20210128101010.0 cr unu---uuuuu 210128e20150501xx s 000 0 eng 10.1007/s00034-014-9917-z doi (NATIONALLICENCE)springer-10.1007/s00034-014-9917-z A New Approach for Gate-Level Delay-Insensitive Asynchronous Logic [Elektronische Daten] [Zhao Wang, Xiao He, Carl Sechen] We present a new approach for gate-level delay-insensitive asynchronous logic. The new approach uses only conventional synchronous synthesis and computer-aided design tools, as well as conventional standard cell libraries. This new design approach is highly suitable for very low voltage operation compared with traditional static CMOS design. An auto-sleep mode together with supply voltage control logic reduces leakage power consumption. Several benchmark circuits are implemented using IBM 130nm technology to show that the new asynchronous logic approach is robust even when operating in the sub-threshold regime. The layout for each benchmark is generated using Cadence's automatic placement and routing tool. Hspice simulations for both asynchronous and synchronous versions of the benchmark circuits enabled comparison of the delay, area and leakage current. Monte Carlo simulations are performed for each benchmark circuit to demonstrate delay insensitivity for very low supply voltages with substantial threshold voltage ( $$V_{T}$$ V T ) variations. Springer Science+Business Media New York, 2014 Asynchronous circuit nationallicence Low voltage operation nationallicence Low leakage nationallicence Wang Zhao The University of Texas at Dallas, 75080, Richardson, TX, USA aut He Xiao The University of Texas at Dallas, 75080, Richardson, TX, USA aut Sechen Carl The University of Texas at Dallas, 75080, Richardson, TX, USA aut Circuits, Systems, and Signal Processing Springer US; http://www.springer-ny.com 34/5(2015-05-01), 1431-1459 0278-081X 34:5<1431 2015 34 34 https://doi.org/10.1007/s00034-014-9917-z text/html Onlinezugriff via DOI BK010053 XK010053 XK010000 Metadata rights reserved Springer special CC-BY-NC licence nationallicence 1 research-article jats NATIONALLICENCE NATIONALLICENCE NL-springer NATIONALLICENCE 856 40 https://doi.org/10.1007/s00034-014-9917-z text/html Onlinezugriff via DOI NATIONALLICENCE 700 1- Wang Zhao The University of Texas at Dallas, 75080, Richardson, TX, USA aut NATIONALLICENCE 700 1- He Xiao The University of Texas at Dallas, 75080, Richardson, TX, USA aut NATIONALLICENCE 700 1- Sechen Carl The University of Texas at Dallas, 75080, Richardson, TX, USA aut NATIONALLICENCE 773 0- Circuits, Systems, and Signal Processing Springer US; http://www.springer-ny.com 34/5(2015-05-01), 1431-1459 0278-081X 34:5<1431 2015 34 34