caa a22 4500 606206345 CHVBK 20210128101011.0 cr unu---uuuuu 210128e20150501xx s 000 0 eng 10.1007/s00034-014-9919-x doi (NATIONALLICENCE)springer-10.1007/s00034-014-9919-x High Performance VLSI Architecture for Three-Step Search Algorithm [Elektronische Daten] [Rohan Mukherjee, Keyur Sheth, Anindya Dhar, Indrajit Chakrabarti, Somnath Sengupta] Motion estimation is the most computationally intensive part of any video coding standard. The three-step search algorithm is a popular fast search technique to reduce complexity in motion estimation. In this paper, we propose a novel architecture for the three-step search technique that simplifies memory addressing and reduces hardware complexity. The proposed architecture minimizes the area while maintaining the speed requirements for real-time video processing. Implemented in Verilog HDL on Virtex-5 technology and synthesized using Xilinx ISE Design Suite 14.1, the critical path in the hardware is 6.536 ns and the equivalent area is calculated to be 2.3K gate equivalent. Springer Science+Business Media New York, 2014 Motion estimation nationallicence Three-step search algorithm nationallicence VLSI architecture nationallicence Memory addressing nationallicence Mukherjee Rohan Department of Electronics and Electrical Communication Engineering, Indian Institute of Technology Kharagpur, 721302, Kharagpur, West Bengal, India aut Sheth Keyur Department of Electronics and Electrical Communication Engineering, Indian Institute of Technology Kharagpur, 721302, Kharagpur, West Bengal, India aut Dhar Anindya Department of Electronics and Electrical Communication Engineering, Indian Institute of Technology Kharagpur, 721302, Kharagpur, West Bengal, India aut Chakrabarti Indrajit Department of Electronics and Electrical Communication Engineering, Indian Institute of Technology Kharagpur, 721302, Kharagpur, West Bengal, India aut Sengupta Somnath Department of Electronics and Electrical Communication Engineering, Indian Institute of Technology Kharagpur, 721302, Kharagpur, West Bengal, India aut Circuits, Systems, and Signal Processing Springer US; http://www.springer-ny.com 34/5(2015-05-01), 1595-1612 0278-081X 34:5<1595 2015 34 34 https://doi.org/10.1007/s00034-014-9919-x text/html Onlinezugriff via DOI BK010053 XK010053 XK010000 Metadata rights reserved Springer special CC-BY-NC licence nationallicence 1 research-article jats NATIONALLICENCE NATIONALLICENCE NL-springer NATIONALLICENCE 856 40 https://doi.org/10.1007/s00034-014-9919-x text/html Onlinezugriff via DOI NATIONALLICENCE 700 1- Mukherjee Rohan Department of Electronics and Electrical Communication Engineering, Indian Institute of Technology Kharagpur, 721302, Kharagpur, West Bengal, India aut NATIONALLICENCE 700 1- Sheth Keyur Department of Electronics and Electrical Communication Engineering, Indian Institute of Technology Kharagpur, 721302, Kharagpur, West Bengal, India aut NATIONALLICENCE 700 1- Dhar Anindya Department of Electronics and Electrical Communication Engineering, Indian Institute of Technology Kharagpur, 721302, Kharagpur, West Bengal, India aut NATIONALLICENCE 700 1- Chakrabarti Indrajit Department of Electronics and Electrical Communication Engineering, Indian Institute of Technology Kharagpur, 721302, Kharagpur, West Bengal, India aut NATIONALLICENCE 700 1- Sengupta Somnath Department of Electronics and Electrical Communication Engineering, Indian Institute of Technology Kharagpur, 721302, Kharagpur, West Bengal, India aut NATIONALLICENCE 773 0- Circuits, Systems, and Signal Processing Springer US; http://www.springer-ny.com 34/5(2015-05-01), 1595-1612 0278-081X 34:5<1595 2015 34 34